Presented at the International Wafer-Level Packaging Conference (IWLPC), 2009

ABSTRACT

The need to inspect the topside, edge/bevel and backside of wafers at various stages of the semiconductor manufacturing process has been driven by device manufacturers continuing the push to 100% wafer-surface utilization for active die. As a result, the wafer-edge exclusion is becoming a thing of the past. With requirements for improving yield, thereby reducing costs, coming to the forefront, processing challenges are simultaneously increasing. The effect of adding knowledge about topside, bevel and backside-specific process phenomenon can be utilized not only in killer defect detection, but also in process improvement that ultimately drives yield improvement.

Once-new processes such as immersion lithography and deposition of high-k dielectric films have driven the development of wafer edge inspection technologies. As these processes become mainstream to semiconductor manufacturing, the next big drivers for continuous improvement in inspection and metrology equipment (and the application of that equipment) will include the 3D-interconnects (3DIC) initiatives. Interconnects are one of the industry’s most difficult challenges: they involve depositing metal into deep and narrow microscopic holes etched into a chip. 3DIC has specific needs for yield-enhancing information and analysis which can be addressed by the next generation of all-surface inspection equipment.
Wafer-Level and Chip-Scale Packaging brought the concept of re-introducing a “back-end wafer” back into the front-end process for RDL deposition and subsequent steps, and this is being seen again in the 3DIC/TSV development path. There is much key learning in inspection and metrology that can be applied to these parallels, which if shared and applied correctly will result in a shorter learning curve as 3DIC/TSV processes become standardized.

-Rolf Shervey

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