Solid State Technology, July 2005

"The dual-damascene process used to create copper interconnect exhibits nonuniformities in both Cu deposition and removal rates that, if not closely controlled, result in structures of varying thickness or unwanted residual material on the wafer surface. Thickness variations affect resistance, which can cause device failure or degraded performance. Residual interconnect material can create shorts between lines also leading to device failure and yield loss. A nondestructive method for directly measuring the thickness on submicron line-array structures is presented as a way to control Cu deposition and removal rates."

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