As semiconductor device dimensions shrink, chip manufacturers must ensure that their metrology capabilities are adequate to control the manufacturing process. Barrier and seed layers are deposited in vias and lines to prevent copper migration and promote uniform nucleation for the subsequent copper fill. Effective barrier and seed layer deposition is critical to assuring the speed and reliability of copper interconnects, since it prevents copper diffusion and provides a quality nucleation layer for subsequent bulk copper fill.

Among the smallest and most difficult to control dimensions in current device designs are the thicknesses of the barrier and seed layers. At the 32 nm node, barrier layer (Ta/TaN) thicknesses range from 5 nm to 7.5 nm and seed layer thicknesses from 10 nm to 20 nm. Absolute accuracy can be difficult to establish, however, close correlation among multiple techniques builds confidence in the accuracy of the measurement.