Oct 8, 2018 Pasadena, California

Enhancements to Picosecond Acoustic Metrology for Application in FOWLP Process

Johnny Dai

Presentation at IMAPS 51st International Symposium on Microelectronics
5:40am — 6:05am

Fan out wafer level packaging (FO-WLP) has been shown to be very versatile thus lending itself attractive to a wide variety of applications. FOWLP is expected to have the highest growth rate, exceeding $2 billion by 2020 including all platforms [1]. First generation “core” fan-out was geared toward mobile applications and redistribution (RDL) lines were typically 10/10μm (line/space). High density fan out (HDFO) has seen remarkable growth in recent years in large part due to entry/adoption by key players [2-4].

Second generation HDFO processes, which were developed to integrate multiple chips in a single package, use multilevel RDL lines at smaller width and tighter pitch, down to 2/2μm and potentially shrinking even further. As design rules for HDFO approach those of front-end processes, requirements for process control and the need for more accurate and repeatable automated metrology will become a necessity. The thin wafers/substrates used in HDFO processes can be warped significantly at several different steps in the process, most significantly by the mismatch between thermal expansion coefficients of the molding compound and the die. Warpage of 2mm or more will need to be routinely handled. Additionally, the metrology system must be able to measure on product wafers thus requiring a non-contact, non- destructive system capable of measuring on small structures [5]. Picosecond acoustic metrology is a workhorse for metal film thickness measurements in front end wafer fabs.

We previously [6] discussed the configuration changes that were made to adapt the technology to meet packaging needs, including integration of high resolution visible reflectometer for resist measurement and enhancements to vision system to provide dimensional information about the structures. In this paper, we present new data on extendibility of the technology to thinner RDL (< 2µm) and at the same time highlight how we overcome the challenges of accurately measuring RDL films after etch process. Post etch thickness measurements are critical to the RDL performance as they are indicative of final electrical test performance. However, these wafers were characterized by significant surface roughness that posed measurement challenges to meeting P/T ratio of < 10.

The PULSE™ setup was modified to handle these wafers resulting in 2-3X improvement in performance and throughput. In this paper, we will describe the details of the hardware modifications and present comparisons of signal to noise enhancements between the standard configuration vis à vis the new configuration. We have extended the solution to measurements of rough as- plated copper films (5-10µm) in <30µm sites and currently exploring our measurement capability of multi-layer pillar stacks. Repeatability is better than 1 sigma < 0.3%.



  1. Buisson and S. Kumar, "What is driving advanced packaging platforms development?," Chip Scale Review, pp. 32-36, May-June 2016.
  2. J. Lau, “Recent advances and trends in advanced packaging”, Chip Scale Review, pp. 46-54, May-June 2017.
  3. Status of Advanced Packaging Report,” Yole Developpement, June 2017.
  4. C. Kim, Measuring metals,dielectrics, resists and CDs in advanced packaging,” Chip Scale Review, pp27-31, August-September 2017
  5. Fanout: Technologies & Market Trends 2016," Yole, 2016.
  6. J. Dai et al., “Comprehensive In-Line Metrology for Advanced RDL Process Monitoring”, IMAPS 2017