The semiconductor industry has continued to evolve and develop new technologies in order to satisfy the ongoing growth in demand for ever smaller and higher performing devices made possible by Moore’s Law. This growth is driven in large part by consumer demand for personal mobile devices, smaller form factor electronics, and the continuing adoption and adaptation of microelectronics into other areas such as automobile dashboards. As the development of these devices progress and more functionality is added in an ever shrinking space, front end of line development has started to slow down and approach certain physical and economic limits.
Advanced packaging has allowed this continued progression on a different level, with techniques such as flip chip, bumping and other forms of packaging providing yield enhancement, cost savings, and even technological advantages. Advanced packaging has primarily been, until recently, a wafer centric technology in form of wafer-level packaging (WLP). Packaging predominantly rectangular die on a round wafer obviously presents geometric inefficiencies. There is an inherent “square peg, round hole” conundrum that is encountered in this case that leads to wasted exposure area during the lithographic process as these round substrates are passed through steppers. Some of the packages, and by extension, the exposures along the perimeter of the wafers will inevitably will result in partial packages. This in turn negatively impacts throughput, reducing output, lowers yields, and results in higher costs in an industry where margins are already thin. This problem has prompted a growing shift toward panel-level packaging (PLP). Given their rectangular nature, panels are devoid of the aforementioned inefficiencies. Furthermore, as advanced packaging moves toward methods such as 2.5 and 3D packaging, technical challenges are introduced that will require innovative materials, tools and approaches. One such challenge is topography.
Package topography will challenge all three facets of the lithography process. Coating wafers with liquid format materials using traditional methods such as spin coating and slot die coating while maintaining uniform film thicknesses over the severe topographies encountered in modern advanced packaging is extremely problematic. A lot of times, the material used during the lithographic process are dielectrics that are intended to be part of the final device. These photoimageable dielectrics (PID’s) typically require a cure in order to strengthen them and enact their final state. Unfortunately, this cure step can induce many undesired effects. A high shrinkage material will actually exacerbate the previously mentioned issue of topography due to different coefficients of thermal expansion. A material that requires a high temperature and/or long cure will also negatively impact throughput, potentially creating an unnecessary bottleneck in the manufacturing chain.
Fortunately, there are existing solutions to this dilemma that have been refined and optimized for the upcoming transition to PLP. True to the multidisciplinary nature of advanced packaging and lithography, the solutions will have to come from multiple sources. A new photoimageable dielectric material in a dry film format that can be processed using a low temperature cure profile has been proven to contain the necessary traits to solve many of these impending issues and concerns. The lithography stepper system will also play an integral role here. A flexible lithography system that is optimized for panel-level packaging will require many considerations in order deliver the expected and required results in a cost efficient manner. This paper will study and present the pairing of a new photoimageable dielectric material in a dry film laminate format along with the latest lithographic stepper to demonstrate the state of the art, and technical and economic viability of panel-level packaging. Elements critical to the lithographic process (e.g. resolution, depth of focus, exposure latitude, film thickness uniformity and other) will be studied, analyzed and presented.