In the past few years, the semiconductor industry has not only moved from planar to 3D devices such as 3D NAND and FinFET but also to 3D integration to meet the increasing demand for mobility, cloud computing and data storage. The data intensive applications that drove this transition have changed the paradigm for manufacturing. Process control for these 3D devices, both memory and logic, place stringent demands on metrology and inspection particularly in the ability to characterize vertical dimensions. High aspect ratio (HAR) structures that are etched to form the vertical path among stacked gates in 3D NAND pose additional challenges as the complexity increases with shrinking dimensions. Critical processes in 3D NAND include multilayer stack deposition, HAR channel etch, wordline metallization, staircase etch, HAR slit etch, and stair contacts formation. From a metrology perspective, characterization of the hard mask material used to form these structures along with characterizing the CD and profile of the holes are critical. Additionally, from a process integration standpoint word line presents challenges for integration and defect inspection and reduction. Key defects of interest are typically sub-surface (especially voids), buried in the stack, or are residues in high aspect ratio structures [1, 2]. In the case of FinFET, ability to measure fin and gate dimensions accurately and provide accurate feedback to process area is essential to ensure the performance of the device as well as maintain high yield in high volume manufacturing. 3D integration has paved the way to bring together various functionalities (such as CMOS image sensors and high bandwidth DRAM memory) together that provides more functionality in a smaller footprint making it economically attractive. System-on-chip (SOC) designs, such as these, have their own in-line metrology and inspection needs for characterization .