Packaging High-performance Memory Devices
While wire bonding remains the dominant technology for chip-to-package connections, advanced packaging processes are gaining a growing share of the market. The transition away from wire bonding is especially notable in high-performance memory applications, where shorter signal paths, higher speed, smaller form factor and lower power are most valuable. Flip-chip, wafer-level packaging (WLP), fan-out wafer-level packaging (FOWLP), and fan-out panel-level packaging (FOPLP) are now seeing increasing adoption. These advanced packaging methodologies present unique inspection and metrology challenges and opportunities, including through-silicon vias (TSVs), fine-pitch redistribution layers (RDLs), copper pillar bumps, micro-bumps and die-level cracks.