Logic 

Logic devices are the transistor-driven brains that control the digital world. Moore's Law continues to drive the scaling of these devices and, likewise, the challenges to process and process control.

ILD Modulus

Low-k dielectric modulus metrology

Beyond 65nm node, the incorporation of low-k dielectrics as inter layer dielectrics (ILD) in Cu interconnect structures to improve device performance has created a number of challenges. The thermo-mechanical reliability is a concern due to the inherent fragility of these materials. The Young's modulus of the inter level dielectrics (ILD) can be directly correlated to peeling and cracking defects that may not become obvious until the die reaches final packaging.

Accurate measurement of the ILD modulus provides a good predictor of its ability to withstand chemical mechanical planarization (CMP) and packaging stresses and ensures that the final device yield and long term reliability are robust.

Pre/Post CMP

Control of metal deposition and planarization

Chemical mechanical planarization (CMP) is a critical step in the dual damascene process for creating high performance interconnect structures. If line structures are under polished, residual copper or barrier will short out the circuitry resulting in defective dies. However, over polishing increases the line resistance, negatively impacting both the speed and performance of devices. To maintain high yield, it is critical to maintain the copper lines at the desired thickness. Pre-CMP measurements offer insight into pattern dependent plating effects - Cu overburden as well as trench measurements and can be used to fine tune the process.

Accurate in-line technique for detecting process variations and flagging mis-process of as-plated and post-CMP is critical to understanding yield issues especially at wafer edges.

Thin Film Metrology

Angstrom-level Film Metrology

Moore's Law has led device designers and manufacturers to pursue scaling and ever thinner films to reduce die size and thickness. Accurate metrology for transparent and metal thin films is crucial to process control and high yields.

Wafer Stress & Bow

Monitoring wafer stress through various process steps

Significant changes in wafer geometry may occur during processing of the wafer and these changes are often much larger than the geometry variations of the bare wafer. Pre/post film deposition measurements provide information on wafer bow. Measurement of substrate/film thickness is used for calculating the stress (added or removed) during the process step.

This information is critical and can be fed forward to a subsequent lithographic process step for appropriate correction.

Consulting and Applications Services

Rudolph's process control consulting services allow busy manufacturers to focus on production while we examine how to improve the process.

The Rudolph applications teams have over twenty years of experience with hundreds of successful projects worldwide across multiple industries. Contact us today to discuss your application study needs.

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