Logic and Foundry

With continuous scaling of logic devices toward 5nm and beyond, the process control for Fin profile, poly gate profile, source and drain profile, and metal function gate profile become more challenging than ever. Multiple measurement parameters are required to monitor the full profile of each structure.

A broadband multi-channel and multi-technology metrology with a state of art modeling and machine learning engine is a must-have for advanced logic fab yield control.

With quadruple patterning and EUV implementation in logic fabs, process control for patterning is becoming more critical than ever. Localized process variations within devices is also becoming more important due to the loading effect.

A broader process coverage and high sample in-die metrology is vital for a logic fab to achieve better time to yield and time to production.

Chemical mechanical planarization (CMP) is a critical process with applications in the front-end of line (FEOL), middle of line (MOL) and back-end of line (BEOL). Oxide, nitride, & poly silicon CMP steps can be found in FEOL and MOL for shallow trench isolation (STI), inter layer dielectric (ILD), self-aligned contact (SAC) and other process modules. Integrated metrology plays a key role in CMP process control for these FEOL and MOL steps where both under-polishing and over-polishing can lead to yield loss.

CMP is also critical in the BEOL dual damascene process for creating high performance interconnect structures. If line structures are under polished, residual copper or barrier will short out the circuitry resulting in defective dies. However, over polishing increases the line resistance, negatively impacting both the speed and performance of devices. To maintain high yield, it is critical to maintain the copper lines at the desired thickness. Pre-CMP measurements offer insight into pattern dependent plating effects - Cu overburden as well as trench measurements and can be used to fine tune the process.

Accurate in-line technique for detecting process variations and flagging mis-process of as-plated and post-CMP is critical to understanding yield issues especially at wafer edges.

Moore's Law has led device designers and manufacturers to pursue scaling and ever thinner films to reduce die size and thickness. Accurate metrology for transparent and metal thin films is crucial to process control and high yields.